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Topic       : Chips 'n Chips
Author      : Michael Ruge
Version     : chips_x.hyp (01/05/2001)
Subject     : Dokumentation/Hardware
Nodes       : 1505
Index Size  : 35662
HCP-Version : 3
Compiled on : Atari
@charset    : atarist
@lang       : 
@default    : 
@help       : 
@options    : -i -s +zz -t4
@width      : 75
View Ref-File

   After a RESET (power-up or reset button) the cpu (68000/68030)
   will start executing at the address pointed to by locations 4-7
   which is ROM (MCU maps the first 8 bytes of ROM) at $FC0000-7
   (by ROM-TOS 1.00 - 1.04) or $E00000-7 (by ROM-TOS 1.06 - 4.04).
   Location $000004 points to the start of the operating system
   code in ROM. The following sequence is then executed:

    1. Perform a reset instruction (outputs a reset pulse)

    2. Read the longword at cartridge address $FA0000. If the
       data read is a "magic number", execute from the cartridge
       (ROM cartridge instructions take over here). If not, continue

    3. Check for a warm start (see if RAM locations were written),
       initialize the memory controller

    4. Initialize the PSG-Chip (deselect disk drives), setup screen
       rate (50 or 60 Hz), write default values to the color palette
       and set the display pointer to 0x10000
    5. Size both banks of memory

    6. if not a warm start, zero memory

    7. Clear the low 64K of memory and setup operating systemvariables
    8. Set up exception vectors

    9. Initialize the MFP-Chip (Initialize both MFP-Chips on TT030)

   10. Set screen resolution (check the Monitor ID Pins) and enable
       interrupts by bringing the IPL to 3.

   11. Attempt to boot floppy; attempt to boot harddisk, run program 

   12. if no boot disk, the 192/256/512K ROM TOS will bring
       up the desktop.

   Number of Bombs und Meaning

       Bombs    Meaning
         2      Bus Error
         3      Adress Error
         4      Illegal Instruction
         5      Divide by Zero Error
         6      CHK-Exception-CPU Interupt
         7      TRAPV-Exception-CPU Interupt
         8      Privilege Violation-CPU Interupt
         9      TRACE-Exception-CPU TRACE Interupt
        10      Line 1010 Emulator
        11      Line 1011 Emulator
        12-23   Unassigned, should have no occurence
        24      Spurios interupt, Bus error during interupt processing
        25-31   Autovector Interupt, Even numbered vectors are used,
                others should have no occurence
        32-63   Trap Instruction, CPU read instruction which forced
                exception processing
        64-79   MFP Interrupt
        80-255  User Interrupt

     Kapitel Der Systemstart der Rechnerhardware, Seite 1