•  Back 
  •  %Main 
  •  Index 
  •  Tree View 
  •  Cross references 
  •  Help page 
  •  Show info about hypertext 
  •  View a new file 
Topic       : Chips 'n Chips
Author      : Michael Ruge
Version     : chips_x.hyp (01/05/2001)
Subject     : Dokumentation/Hardware
Nodes       : 1505
Index Size  : 35662
HCP-Version : 3
Compiled on : Atari
@charset    : atarist
@lang       : 
@default    : 
@help       : 
@options    : -i -s +zz -t4
@width      : 75
View Ref-File

   Asynchronous - Operating mode in which a memory device responds to 
   input signals whenever they occur. As opposed to synchronous opera-
   tion in which the input signals must be present at specified times
   in the device's clock cycle.
   Auto precharge - A Synchronous DRAM feature that allows the memory
   chip's circuitry to close a page automatically at the end of a burst.
   Auto refresh - Commonly referred to as CAS\ before RAS\ refresh or 
   CE before RE refresh. An internal address counter increments the row
   address each time the memory controller initiates a CAS\ before RAS\
   refresh cycle.
   Burst EDO DRAM - An EDO DRAM with some burst features such as a four
   bit burst length that can be delivered in sequential or interleave 
   Block write - A VRAM feature that allows the user to write 8 columns
   per page cycle. Columns may be masked to permit partial writes.
   Buffering - Adding logic, particularly drivers, to a SIMM or DIMM to
   increase the output current. Buffering is used to overcome signal 
   attenuation due to capacitive loading.
   Burst - Multiple bits of data from a single device accessed in rapid
   succession. Burst lengths vary by product and user application.
   Burst rate - The rate at which data in a burst can be accessed. 
   The burst rate is usually shown as the number of clock cycles requi-
   red for each bit of data in a burst. For example, the burst rate for
   a 4-bit burst on an SRAM operating at microprocessor speed would be 
   shown as 2/1/1/1 or two cycles for the first bit, and one additional
   cycle for each subsequent bit.
   Byte-write - A memory operation in which one or more bytes on a data
   bus are masked during a store operation so that only particular bytes
   are accessed and written to. Byte write may be used in SRAM and DRAM 
   Cache -  A small amount of memory (usually SRAM) used to temporarily
   store data. Properly designed, a cache improves system performance by
   reducing the need to access the system's main memory for every trans-
   CAS (Column Address Select) - A control pin on a DRAM used to latch
   and activate a column address. The column selected on a DRAM is deter-
   mined by the data present at the address pins when CAS becomes active.
   Check bits - Extra data bits provided by a DRAM module to support ECC
   function. For a 4-byte bus, 7 or 8 check bits are needed to implement
   ECC, resulting in a total bus width of 39 or 40 bits. On an 8-byte bus,
   8 additional bits are required, resulting in a bus width of 72 bits.
   DRAM DIMM - Dual Inline Memory Module. DIMMs are small memory cards
   with data buses of 64, 72, or 80 bits. Unlike SIMMs, DIMMS have func-
   tionally unique contacts on the front and back of the card. Designed 
   to meet JEDEC standards, DIMMs come with a variety of sizes, speeds, 
   and features.
   ECC (Error Correction Code9 - ECC is logic designed to correct memory
   errors. The number of errors that can be corrected depends upon the
   algorithms used, and the number of error correction bits (non-data 
   bits) present. This logic may be included on a SIMM, or it may be 
   found on one of the computer's circuit boards.
   ECC on SIMM - SIMMs, featuring on-board ECC logic, designed to be
   plug compatible with parity based SIMMs. The ECC logic corrects single 
   errors in each byte of SIMM data.
   EDO (Extended Data Out) - A DRAM performance feature that permits 
   multiple bits of data in a single row to be accessed quickly. EDO
   involves selecting multiple column addresses in rapid succession 
   once the row address has been selected. Once the first column address
   has been selected and CAS becomes active, the data output drivers are
   activated. The data output drivers remain active for each successive
   CAS strobe, until RAS goes high.

     Kapitel Das DRAM Glossar, Seite 1