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Topic       : Chips 'n Chips
Author      : Michael Ruge
Version     : chips_x.hyp (01/05/2001)
Subject     : Dokumentation/Hardware
Nodes       : 1505
Index Size  : 35662
HCP-Version : 3
Compiled on : Atari
@charset    : atarist
@lang       : 
@default    : 
@help       : 
@options    : -i -s +zz -t4
@width      : 75
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   FPM (Fast Page Mode) - A timing option that permits several bits 
   of data in a single row on a DRAM to be accessed at an accelerated 
   rate. Fast Page Mode involves selecting multiple column addresses 
   in rapid succession once the row address has been selected. Each 
   time a column address is selected and CAS becomes active, the data
   output drivers are activated; each time CAS goes high, the data 
   output drivers are deactivated.
 
   Interleave - The process of taking data bits (singly or in bursts)
   alternately from two or more memory pages (on an SDRAM) or devices
   (on a memory card or subsystem).
 
   Keys - Notches in a memory module (DRAM DIMM or SIMM) that prevent
   them from being plugged into an incompatible system. For example, 
   a DIMM keyed for 3.3V operation cannot be plugged into a socket 
   designed for use with a 5V system.
 
   Parity - Logic that detects the presence of an error in memory. 
   Generally, a single parity bit is used for each byte (8 bits) of 
   data. The most commonly used forms of parity are even parity, odd
   parity, and checksums.
 
   Pipeline - In DRAMs and SRAMs, a method for increasing the performance
   using multistage circuitry to stack or save data while new data is 
   being accessed. The depth of a pipeline varies from product to product.
   For example, in an EDO DRAM, one bit of data appears on the output 
   while the next bit is being accessed. In some SRAMs, pipelines may 
   contain bits of data or more.
 
   RAS - Row Address Select. A control pin on a DRAM used to latch and 
   activate a row address. The row selected on a DRAM is determined by the
   data present at the address pins when RAS becomes active.
 
   Refresh - The process used to restore the charge in DRAM memory cells
   at specified intervals. The required refresh interval is a function of
   the memory cell design and the semiconductor technology used to manu-
   facture the memory device.

























     Kapitel Das DRAM Glossar, Seite 2